Silicon design, verification & signoff
Analog Layout Services
Custom analog and standard cell layout for advanced nodes.
We provide high-quality custom analog and mixed-signal IC layout services for developing high-performance mixed-signal, RF, SerDes, PLL, PMIC and custom analog cells.
Our layout engineers combine a deep understanding of device physics, process technologies, parasitic effects, device matching, symmetry, noise coupling, IR drop, electromigration and manufacturing constraints to deliver robust, silicon-proven layouts across advanced technology nodes.
From individual analog IP blocks to complete mixed-signal macros, we support customers throughout the physical implementation and verification cycle.
Capabilities
- Transistor-Level Layout
- Full-Custom Layout
- Analog IP Layout
- Mixed-Signal Layout
- Custom Device Layout
- Hierarchical Layout
- Block-Level Layout
- Top-Level Integration
- Layout Optimization
Physical Verification
- DRC
- LVS
- ERC
- Antenna Checks
- Density Checks
- EM/IR
- Latch-up
- PERC
SerDes
- Rx Layout
- Tx Layout
- CTLE
- DFE
- Clocking Layout
- Serializer
- Deserializer
- PLL
- VCO
- Charge Pump
Power Management (PMIC)
- LDO
- Bandgap
- Power Switch
- Reference Circuits
- ESD Circuits
- Driver & Pre-Driver
Data Converters
- ADC
- DAC
RF Circuits
- LNA
- Mixer
- TIA
Advanced Node Expertise
- TSMC N2 / N3 / N5
- Samsung SF2 / SF4
- Intel 18A
Let’s build your next chip
Tell us what you’re designing. We’ll usually come back within a day with how we’d de-risk and accelerate it.